Bulk CMOS technologies are predicted to face crucial technological challenges in the next decade. At the same time, novel devices based on Resistive Switching Materials (RSM) do not suffer from the same constraints and are expected to play a primary role as devices in future ultra-large scale integration technologies, for both memory and logic applications.
The interest in these devices is motivated not only by their small size, but also their superior characteristics, such as non-volatile memory storage, two-terminal connection and excellent scalability down to the 1 nm range. The RSM, specifically, plays a major role in the current efforts towards effective implementation of the device for practical applications, with manufacturers currently exploring resistive switching materials as future bricks for stand-alone memories as well as for applications in neuromorphic circuits as well as logic-in-memory.
TaOx/CrOy ReRam Element—Background
In literature, transition-metal oxide memory technologies base their working principle on the change of their resistance state due to a modification of the conductivity property of the oxide itself. Two major groups of transition metal oxide-based resistive switching elements can be identified by considering the physical mechanism that drives the modification of the resistance state.
The first group consists of two-terminal devices based on metal/oxide switches, such as SiO2, HfO2 [1] or Al2O3 [2]. These devices behave as solid-state electrochemical switches, the resistance of which is defined by a metallic filament formation mechanism related to the solid-state redox reactions stimulated by the applied electric field [3]. The writing mechanism does not require opposite voltage polarities. This mechanism is also known as unipolar.
A second group is related to the vacancy redistribution in transition metal oxide (MOx, where M denotes the transition metal, O denotes oxygen and the x is a stochiometric number) layers upon applying a voltage and it causes the switching from an insulating to a metallic state. For instance, considering TiO2, the diffusion of oxygen vacancies transforms the TiO2 volume into a highly conductive TiO2-x layer, thus reducing the total resistance of the oxide layer. Upon application of an electric field with opposite polarity, the redistribution of oxygen vacancies is led toward the opposite electrode and total resistance is increased again as the proportion of stochiometric TiO2 increases with respect to TiO2-x Since the writing of this cell relies on the application of opposite voltage polarities, the writing mechanism is often labeled as bipolar. Note that the unipolar or bipolar nature of the switching functionality in MOx depends also on the chemical nature of the top and bottom electrodes [4].
To summarize the state-of-the-art, note that the resistive memories are composed of an oxide mono-layer stacked between 2 metal electrodes.
Generic Memory Structure and Complementary Resistive Programming—Background
Future deeply scaled circuits will see their performances limited by the physical limitations of the materials. To keep pushing the performance of computation and the density of storage, the microelectronics industry envisages using more efficient state variable than the electronic charge. When considering the resistive switching materials, excellent scalability and programming time can be obtained if compared to traditional Flash. This is related to the fact that RSM can be arranged are simple two-terminal resistive switching devices [1A, 2A].
While a lot of research effort targets high density RSM-based standalone memories [3A], one aim of the present invention is the usage of RSM devices for Field-Programmable Gate Arrays (FPGAs). The reason behind this choice is that in reconfigurable logic, up to 40% of the area is dedicated to the storage of configuration signals [4A]. Traditionally, the configuration data is serially loaded in SRAM cells, distributed throughout the circuit [5A]. As a consequence, circuit power on is limited by slow serial configuration. To overpass SRAM volatility and loading time, Flash NVM have been proposed [6A]. Nevertheless, the use of a hybrid CMOS-Flash technology results in high fabrication cost. Conversely, RSM devices are fabricated within the Back-End-of-the-Line (BEoL) metal lines, moving the configuration memory to the top of the chip and reducing the area utilization[7A]. Similarly, the RSM devices can be utilized in combination with Through-Silicon-Via (TSVs), enabling 3-D stacked FPGA architectures [8A].
With the recent development of RSM technology, a number of novel FPGA building blocks and architectures have been proposed in the past few years. For example, routing structures based on RSM devices have shown promise. In [9A], a cross point for switch-boxes, using the RSM devices as non-volatile switches, is proposed to route signals through low-resistive paths, or to isolate them by means of high-resistive paths. The concept of routing elements based on RSM switches was then exploited in [10A, 11A] for timing optimization in FPGAs.
The present invention appear to offer a complete proof of concept of a RSM-based Generic Memory Structure (GMS) circuit for FPGAs from technology development to architectural evaluation. The main idea is to replace the pass-transistors in SRAM-based FPGAs by RSMs. Hence, the RSMs store the information in their resistive states and can be used either to route signals through low-resistive paths, or to isolate them by means of high-resistive paths. Such functionality is used to build either routing Multiplexers (MUXs) or configuration nodes. In order to keep the programming complexity as per SRAM-based FPGAs, we propose an efficient methodology based on the Generic Memory Structure (GMS) complementary programming. The proposed methodology has been validated by electrical measurements on a fabricated GMS device. Finally, the impact of the GMS MUXs and configuration memories is studied at the system level over a set of complex benchmarks. We show that the GMS-based FPGA reduces area by 7%, while the low on-resistance of RSM devices provide a gain of 58% in delay compared to SRAM-based counterpart.
Read/Write Circuitry—Background
In order to gain full advantages of the RSM device arrays, it is crucial for the integration to be CMOS compatible, having a thermal budget compatible with CMOS Back-End-of-the-Line (BEoL) and the possibility for the memory array to be integrated into a CMOS chip by post-processing. It is thus crucial that a dedicated read/write circuit is able to tackle the issues coming from RSM device arrays and specifically implement a dedicated read/write protocol.